In video coding standards, a compliant bit stream must be able to be decoded by a hypothetical reference decoder that may be conceptually connected to the output of an encoder and consists of at least a pre-decoder buffer, a decoder and an output/display unit. This virtual decoder is known as the hypothetical reference decoder (HRD) in e.g. H.263, H.264/AVC and H.265/HEVC, and the video buffering verifier (VBV) e.g. in MPEG-4 Part 2. The virtual decoder and buffering verifier are collectively called as hypothetical reference decoder (HRD) in this document. A stream is compliant if it can be decoded by the HRD without buffer overflow or, in some cases, underflow. Buffer overflow happens if more bits are to be placed into the buffer when it is full. Buffer underflow happens if some bits are not in the buffer when said bits are to be fetched from the buffer for decoding/playback.
HRD models typically include instantaneous decoding, while the input bitrate to the coded picture buffer (CPB) of HRD may be regarded as a constraint for the encoder and the bitstream on decoding rate of coded data and a requirement for decoders for the processing rate. The CPB operates in a serial fashion, i.e. decodes data units, such as coded pictures or H.265/HEVC decoding units, in their decoding or bitstream order. Consequently, the HRD models do not support parallel processing, where more than one processing unit, such as a processor or a core in a multi-core processor, decodes data. Therefore, timing and/or bitrate information are only provided for serial processing considerations.
One of the motivations for the HRD is to avoid so-called evil bitstreams, which would consume such a large quantity of resources that practical decoder implementations would not be able to handle. However, with the serial processing considerations in the HRD make it impossible to ensure that a single processing unit within a parallel decoding arrangement including multiple processing units would not be loaded with an evil bitstream portion consuming too large a quantity of resources. Moreover, timing and delays are indicated for serial processing only, and said timing information as well as HRD buffer sizes is used in many decoder implementations. This makes it harder or impossible to use signalled HRD buffer sizes and timing information in decoder implementations using multiple processing units.
Therefore, there is a need for a more optimal method for utilizing the HRD models.